LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
FUM00701
59
5.2 Software Design Considerations
5.2.1 WSM (Write State Machine) Polling
The status register bit SR.7 provides a software method of
detecting block erase, full chip erase, (page buffer)
program and OTP program completion. After the Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command is written to the CUI (Command User
Interface), SR.7 goes to "0". It will return to "1" when the
WSM (Write State Machine) has completed the internal
algorithm.
The status register bit SR.7 is "1" state when the device is
in the following mode.
• The device can accept the next command.
• Block erase is suspended and (page buffer) program
operation is not executed.
• (Page buffer) program is suspended.
• Reset mode
5.2.2 Attention to Program Operation
Do not re-program "0" data for the bit in which "0" has
been already programmed. This re-program operation
may generate the bit which cannot be erased.
To change the data from "1" to "0", take the following
steps.
• Program "0" for the bit in which you want to change
the data from "1" to "0".
• Program "1" for the bit in which "0" has been already
programmed.
(When "1" is programmed, erase/program operations
are not executed onto the memory cell in flash
memory.)
For example, changing the data from "10111101" to
"10111100" requires "11111110" programmed.
5.3 Data Protection Method
Noises having a level exceeding the limit specified in the
specification may be generated under specific operating
conditions on some systems. Such noises, when induced
onto WE# signal or power supply, may be interpreted as
false commands and causes undesired memory updating.
To protect the data stored in the flash memory against
unwanted writing, systems operating with the flash
memory should have the following write protect designs,
as appropriate:
The below describes data protection method.
1) Protection of data in each block
• ny locked block by setting its block lock bit is
protected against the data alternation. When WP# is
VIL, any locked-down block by setting its block lock-
down bit is protected from lock status changes.
By using this function, areas can be defined, for
example, program area (locked blocks), and data area
(unlocked blocks).
• For detailed block locking scheme, refer to Sections
4.12 to 4.14.
2) Protection of data with VPP control
• When the level of VPP is lower than VPPLK (VPP
lockout voltage), write functions to all blocks
including OTP block are disabled. All blocks are
locked and the data in the blocks are completely
protected.
3) Protection of data with RST#
• Especially during power transitions such as power-up
and power-down, the flash memory enters reset mode
by bringing RST# to VIL, which inhibits write
operation to all blocks including OTP block.
• For detailed description on RST# control, refer to
Section 5.1.5.
Protection against noises on WE# signal
To prevent the recognition of false commands as write
commands, system designer should consider the method
for reducing noises on WE# signal.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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