LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
FUM00701
60
5.4 High Performance Read Mode
5.4.1 CPU Compatibility
LH28F320BX/LH28F640BX series supports two high-
performance read modes for the parameter and main
blocks:
• Asynchronous read mode in which 8-word page mode
is available
• Synchronous burst mode
These two read modes provide much higher read accesses
than was previously used.
The asynchronous read mode is suitable for non-clocked
memory systems and is compatible with standard page-
mode ROM. If the memory subsystem has access to an
external processor referenced clock, the synchronous
burst mode is available for increased read performance.
The clock frequency for synchronous burst mode is
described in specifications. If the system CPU or ASIC
does not support page-mode or burst accesses, single
asynchronous and synchronous read modes can be used.
It depends on the setting in the read configuration register
which read mode is available. When the read
configuration register bit RCR.15 is set to "1", the device
is in asynchronous read mode. If the bit RCR.15 is set to
"0", the device is in synchronous burst mode. Upon reset,
the device defaults to asynchronous read mode and is put
into read array mode.
5.4.2 Features of ADV# and CLK
ADV# and CLK pins are important for synchronous burst
mode.
• ADV# can be derived from the processor’s transaction
start signal. If the processor does not have this type of
signal, other standard CPU control signals can be used
to control ADV#. ADV# must toggle to inform the
flash memory to latch a new address.
If this signal is not used in asynchronous read mode,
CE# must toggle to inform the flash memory of a new
address.
• CLK can be derived from the processor’s memory
clock output. If the processor does not supply this
control signal to the memory subsystem, the signal
can be received from the clock signal generator
through a clock buffer. This buffer minimizes clock
load and skew.
5.4.3 Address Latch
The internal address latch latches the address for read and
write operations. The address latch is controlled by
ADV#. When ADV# is VIL, the latch is open. The latch
closes when ADV# is driven high or upon the first rising
(or falling) edge of CLK while ADV# is VIL. This stores
the current address on the bus into the flash memory
device and lets the address bus change without affecting
the flash. This pin works the same in write operations; the
address to be written to the CUI is latched on the rising
ADV# edge. Since write operations are asynchronous
mode, CLK is ignored and the address is not latched on
the clock edge. In asynchronous read mode, the address
latch does not need to be used but addresses must then
stay stable during the entire read operation. If ADV# is
not used, which is fixed VIL, in asynchronous mode,
addresses are latched on the rising edge of CE# during
reads and on the rising edge of CE# or WE# whichever
goes high first during writes.
5.4.4 Using Asynchronous Page Mode
After initial power-up or reset mode, the device defaults
to asynchronous read mode in which 8-word page mode
is available. The asynchronous page mode is available for
the parameter and main blocks, and is not supported from
other locations within the device, such as the status
register, identifier codes, OTP block and query codes. In
asynchronous page mode, CLK is ignored and ADV#
must be held VIL throughout the page access. Holding
ADV# VIL allows new page mode accesses. The initial
valid address will store 8 words of data in the internal
page buffer. Each word is then output onto the data bus by
toggling the address A2-0.
If the asynchronous page mode is only used, CLK and
ADV# can be tied to GND. Holding CLK and ADV#
GND will minimize the power consumed by these two
pins and will simplify the interface, making it compatible
with standard flash memory and industry standard page
mode ROMs. With ADV# at VIL, the addresses cannot be
latched into the device. Therefore, addresses must stay
valid throughout the entire read cycle until CE# goes to
VIH. Figure 18 shows a waveform for asynchronous page
mode read timing with ADV# held low. Note that the
address A2-0 must be toggled to output the page-mode
data.
In asynchronous read mode, the output of WAIT# is fixed
to VOH.
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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