LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
FUM00701
61
5.4.5 Using Synchronous Burst Mode
Synchronous burst mode provides a performance increase
over asynchronous read mode. It supports effective zero
wait-state performance up to the frequency described in
specifications. The synchronous burst mode is available
for the parameter and main blocks, and is not supported
from other locations within the device, such as the status
register, identifier codes, OTP block and query codes. It is
not possible to do a synchronous burst read across the
partition boundary. Figure 19 illustrates a waveform for
synchronous burst mode read timing. The valid addresses
are asserted, and then the device will output the first data
after certain delay time. Subsequent data will be output
every CLK cycle.
There are two different considerations for an external
interface logic whether or not the processor supports
synchronous burst mode at boot-up.
• Case 1, the processor does not support synchronous
burst mode at boot-up, but rather boots up in
asynchronous read mode. This is the initial mode of
the flash memory, so no special design considerations
need to be made. After booting up, the processor can
configure the read configuration register for
synchronous burst mode.
• Case 2, the processor does support synchronous burst
mode at boot-up. After return from reset, the flash
memory defaults to asynchronous read mode, which is
inherently slower than synchronous burst mode.
External interface logic will be needed to inform the
processor of this, and to insert wait states to match the
flash memory’s timing with the processor’s timing.
This logic is only necessary until the processor has a
chance to set the flash memory device to synchronous
burst mode, at which time the external logic must be
notified of this change. This can be accomplished via
a write-able register within the system wait-state logic
or via a general purpose I/O (GPIO) pin. The GPIO
pin may operate as an input into the system logic.
5.4.6 Using WAIT# in Burst Mode
LH28F320BX/LH28F640BX series supports 4-word, 8-
word and continuous burst modes. In continuous burst
mode or 4-, 8-word burst with no-wrap (RCR.3="1")
mode, WAIT# informs the system CPU whether output
data is valid or not (refer to Section 4.16.8.1).
• WAIT#="1": there is valid data on the bus.
• WAIT#="0": the data on the bus is invalid.
When the output delay is encountered, the WAIT# pin
will be asserted at a logic "0". This signal should be fed
into the systems wait-state control logic or directly to the
CPU. The WAIT# output pin is gated by CE# and OE#. If
either CE# or OE# go to VIH, the WAIT# output buffer
turns off. An internal pull-up resistor holds WAIT# at a
logic "1" state. Figure 20 shows a waveform for an output
delay timing with ADV# at a logic "0".
WAIT# can be configured for assertion during the delay
or one data cycle before the delay by setting the read
configuration register bit RCR.8.
5.4.7 Single Read Mode
The following data can only be read in single
asynchronous read mode or single synchronous read
mode.
• Status register
• Query code
• Manufacturer code
• Device code
• Block lock configuration code
• Read configuration register code
• Partition configuration register code
• OTP block
A waveform of read timing for single asynchronous read
mode and single synchronous read mode are shown in
Figure 21 and Figure 22, respectively.
Single asynchronous read mode is compatible with
previous SHARP flash memory devices. CLK is ignored
in this mode. The valid addresses are asserted, and then
the device will output data after certain delay time, such
as tAVQV, tVLQV, tELQV or tGLQV. Addresses are latched
on the rising edge of ADV#. If ADV# is held VIL,
addresses must stay valid throughout the entire read cycle
until CE# goes to VIH.
In single synchronous read mode, after the valid
addresses are asserted, the corresponding data will be
output on the rising or falling edge of CLK, which is
determined by the read configuration register bit RCR.6.
Addresses are lathed when ADV# is driven high or upon
the rising or falling edge of CLK while ADV# is VIL. 4-
word, 8-word or continuous burst accesses is not
available in this mode. Therefore, the external input
addresses must be incremented every read cycle.
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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