LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
(40µA + 8 • IDRN) current pull-up. As the load capacitor
nears full charge, load current begins to decline. At point
8, the load current falls and the SENSE voltage drops below
VACL(t). The analog current limit loop shuts off and the
GATE pin ramps further. At time point 9, the SENSE voltage
drops below VCB and the fault TIMER cycle ends, followed
by a 5µA discharge cycle (cool off). When GATE ramps
past VGATEH threshold at time point 10, PWRGD pulls low.
At time point 11, GATE reaches its maximum voltage as
determined by VIN.
Undervoltage Timing
In Figure 10 when the UV pin drops below VUVHI – VUVHST
(time point␣ 1), the LTC4214 shuts down with TIMER, SS
and GATE all pulling low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV recovers and clears VUVHI (time point 2), an
initial timer cycle begins followed by a start-up cycle.
UV DROPS BELOW VUVHI – VUVHST. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
2
3 4 56 7 8 9 10 11
UV
VUVHI –
VUVHST
VUVHI
TIMER
5µA
VTMRH
40µA + 8 • IDRN
5µA
VTMRL
5µA
GATE
SS
VGATEL
SENSE
50µA
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
50µA
VIN – VGATEH
VACL
VCB
DRAIN
VDRNCL
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F10
Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)
421412f
22
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