LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
Overvoltage Timing
During normal operation, if the OV pin exceeds VOVHI as
shown at time point 1 of Figure 12, the TIMER and PWRGD
status are unaffected. Nevertheless, SS and GATE pull
down and the load is disconnected. At time point 2, OV
recovers and drops below the VOVHI – VOVHST threshold. A
GATE start-up cycle begins. If the overvoltage glitch is
long enough to deplete the load capacitor, a full start-up
cycle as shown between time points 4 through 7 may
occur.
OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED
OV DROPS BELOW VOVHI – VOVHST, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
2 34 5 67 8 9
OV
TIMER
GATE
SS
SENSE
VOVHI
VOVHI – VOVHST
VTMRH
40µA + 8 • IDRN
5µA
VGATEL
50µA
50µA
VIN – VGATEH
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
VACL
VCB
GATE
START-UP
5µA
4214 F12
Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE)
421412f
24
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