LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
Analog Current Limit and Fast Current Limit
In Figure 16a, when SENSE exceeds VACL, GATE is regu-
lated by the analog current limit amplifier loop. When
SENSE drops below VACL, GATE is allowed to pull up. In
Figure 16b, when a severe fault occurs, SENSE exceeds
VFCL and GATE immediately pulls down until the analog
current amplifier can establish control. If the severe fault
causes VOUT to exceed VDRNCL, the DRAIN pin is clamped
at VDRNCL. IDRN flows into the DRAIN pin and is multiplied
by 8. This extra current is added to the TIMER pull-up
current of 40µA. This accelerated TIMER current of
[40µA+8 • IDRN] produces a shorter circuit breaker fault
delay. Careful selection of CT, RD and MOSFET can help
prevent SOA damage in a low impedance fault condition.
CB TIMES OUT
12 34
40µA + 8 • IDRN
TIMER
VTMRH
5µA
5µA
1
2
VTMRH
40µA + 8 • IDRN
TIMER
GATE
GATE
SS
SENSE
VACL
VCB
SS
SENSE
VFCL
VACL VCB
VOUT
DRAIN
VOUT
VDRNCL
DRAIN
PWRGD
(16a) Analog Current Limit Fault
PWRGD
4214 F16
(16b) Fast Current Limit Fault
Figure 16. Current Limit Behavior (All Waveforms are Referenced to VEE)
421412f
28
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