LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
VIN Undervoltage Lockout Timing
The VIN undervoltage lockout comparator, UVLO, has a
similar timing behavior as the UV pin timing except it looks
for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When VIN exits undervoltage
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
In Figure 11, both UV and OV pins are connected together.
When UV clears VUVHI (time point 1), an initial timing
cycle starts. If the system bus voltage overshoots VOVHI
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the VOVHI
– VOVHST threshold. The initial timing cycle restarts,
followed by a GATE start-up cycle.
UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE
UV/OV DROPS BELOW VOVHI – VOVHST AND TIMER RESTARTS INITIAL TIMING CYCLE
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
12 3
10 12
4 5 67 8 9 11
UV/OV
VOVHI
VUVHI
VOVHI – VOVHST
TIMER
VTMRH
5µA
40µA + 8 • IDRN
5µA
VTMRL
5µA
GATE
SS
SENSE
VGATEL
50µA
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
50µA
VIN – VGATEH
VACL
VCB
DRAIN
VDRNCL
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F11
Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
421412f
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