MSM5718B70 View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM5718B70' PDF : 40 Pages View PDF
MSM5718B70
¡ Semiconductor
RECOMMENDED TIMING CONDITIONS
Symbol
tCR, tCF
tCYCLE
tTICK
tCH, tCL
tTR
tDR, tDF
tQR, tQF
tS
tH
tREF
tLOCK,RESET
tLOCK,POWERUP
(Ta = 0˚C to 70˚C)
Parameter
Min.
Max. Unit
TxClk and RxClk input rise and fall times
0.3
0.8
ns
TxClk and RxClk cycle times
3.33/3.75/4.0 4.5
ns
Transport time per bit per pin (this timing interval is
synthesized by the RDRAM's internal clock generator)
TxClk and RxClk high and low times
0.5 (2 ns @ 0.5 (2.25 ns @
tCYCLE = 4ns) tCYCLE = 4.5ns)
tCYCLE
45%
55%
tCYCLE
TxClk-RxClk differential
0
0.7
tCYCLE
Data/Control input rise and fall times
0.3
0.6
ns
Data/Control output rise and fall times
0.3
0.5
ns
Data/Control-to-RxClk setup time
0.35
—
ns
RxClk-to-Data/Control hold time
0.35
—
ns
Refresh interval
—
17
ms
RDRAM internal clock generator lock time from Reset
mode
—
RDRAM internal clock generator lock time from PowerUp
mode
—
750 (3 ms @
tCYCLE = 4ns)
750 (3 ms @
tCYCLE = 4ns)
tCYCLE
tCYCLE
28
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