PRELIMINARY
256Mb: x32
SDRAM
SINGLE READ – WITHOUT AUTO PRECHARGE1
T0
T1
T2
T3
T4
T5
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
PRECHARGE
NOP
ACTIVE
DQM /
DQML, DQMH
A0-A9, A11
tAS tAH
ROW
tCMS tCMH
COLUMN m2
ROW
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
ALL BANKS
DISABLE AUTO PRECHARGE SINGLE BANK
BANK
BANK
ROW
BANK
DQ
tRCD
tRAS
tRC
tAC
tLZ
CAS Latency
tRP
tOH
DOUTm
tHZ
DON’T CARE
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.