MT48LC8M32B2B5-6 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC8M32B2B5-6' PDF : 55 Pages View PDF
WRITE – WITHOUT AUTO PRECHARGE1
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
DQM 0-3
tCMS tCMH
A0-A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
COLUMN m3
DISABLE AUTO PRECHARGE
BANK
tDS tDH
tDS tDH
DQ
tRCD
tRAS
tRC
DIN m
DIN m + 1
T4
NOP
tDS tDH
DIN m + 2
T5
T6
NOP
PRECHARGE
ALL BANKs
SINGLE BANK
BANK
tDS tDH
DIN m + 3
t WR 2
PRELIMINARY
256Mb: x32
SDRAM
T7
T8
NOP
ACTIVE
ROW
ROW
BANK
tRP
NOTE:
1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A9 and A11 = “Don’t Care.”
4. tWR of 1 CLK available if running 100 MHz or slower. Check factory for availability.
DON T CARE
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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