MT48LC8M32B2B5-6 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC8M32B2B5-6' PDF : 55 Pages View PDF
PRELIMINARY
256Mb: x32
SDRAM
READ – FULLL-PAGE BURST1
T0
CLK
tCKS tCKH
CKE
T1
tCL
tCH
tCMS tCMH
COMMAND
ACTIVE
NOP
T2
tCK
READ
DQM 0-3
tCMS tCMH
A0-A9, A11
tAS tAH
ROW
tAS tAH
A10
ROW
BA0, BA1
tAS tAH
BANK
COLUMN m 2
BANK
T3
NOP
DQ
tRCD
tAC
tLZ
CAS Latency
NOTE: 1. For this example, the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
3. Page left open; no tRP.
T4
NOP
T5
NOP
T6
( ( Tn + 1
))
((
))
((
))
((
))
((
))
NOP ( (
))
((
))
((
))
NOP
Tn + 2
Tn + 3
BURST TERM
NOP
Tn + 4
NOP
tAC
tOH
Dout m
tAC
tOH
DOUT m+1
((
))
((
))
((
))
((
))
((
))
((
))
tAC ( (
))
tOH
((
))
DOUT m+2( (
))
tAC
tOH
DOUT m-1
tAC
tOH
DOUT m
256 locations within same row
Full page completed
Full-page burst does not self-terminate.
Can use BURST TERMINATE command. 3
tOH
DOUT m+1
tHZ
DON’T CARE
UNDEFINED
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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