MT48LC8M32B2B5-6 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC8M32B2B5-6' PDF : 55 Pages View PDF
PRELIMINARY
256Mb: x32
SDRAM
READ – WITHOUT AUTO PRECHARGE1
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
DQM 0-3
tAS tAH
A0-A9, A11
ROW
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m 2
DISABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tAC
tLZ
CAS Latency
T4
NOP
tAC
tOH
DOUT m
T5
T6
NOP
PRECHARGE
tAC
tOH
DOUT m + 1
ALL BANKS
SINGLE BANK
BANK
tAC
tOH
DOUT m + 2
tRP
T7
NOP
tOH
DOUT m + 3
tHZ
T8
ACTIVE
ROW
ROW
BANK
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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