P2V28S20ATP-7 View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'P2V28S20ATP-7' PDF : 51 Pages View PDF
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /
CAS= L, /WE= /CKE= H) command. The refresh address is gen-
erated internally. 4096 REFA cycles within 64ms refresh 64M bit
memory cells. The auto-refresh is performed on 4 banks
concurrently. Before performing an auto-refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is mini-
mum tRC. Any command must not be supplied to the device be-
fore tRC from the REFA command.
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Auto-Refresh
NOP or DESELECT
minimum tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
JULY.2000
Page-27
Rev.2.2
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