P2V28S20ATP-7 View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'P2V28S20ATP-7' PDF : 51 Pages View PDF
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command
(/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-
refresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and
the only enabled input ,all other inputs including CLK are
disabled and ignored, so that power consumption due to
synchronous inputs is saved. To exit the self-refresh, supplying
stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE=H. After tRC from the 1st CLK egde following
CKE=H, all banks are in the idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Stable CLK
NOP
new command
X
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
JULY.2000
Page-28
Rev.2.2
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