PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
7. Functional description
7.1 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external
components are required and the OSC input must be connected to VDD. An external clock
signal, if used, is connected to this input.
7.2 Power-On Reset (POR)
The on-chip Power-On Reset (POR) initializes the chip after power-on or power failure.
7.3 I2C-bus controller
The I2C-bus controller receives and executes the commands. The PCF8531 acts as an
I2C-bus slave receiver and therefore it cannot control bus communication.
7.4 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.5 Display data RAM
The PCF8531 contains 34 × 128 bits static RAM for storing the display data, see Figure 7.
The RAM is divided into 6 banks of 128 bytes (6 × 8 × 128 bits). Bank 5 is used for icon
data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There
is a direct correspondence between the X address and column output number.
7.6 Timing generator
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not affected by operations on the data buses.
7.7 Address counter
The address counter sets the addresses of the display data RAM for writing.
7.8 Display address counter
The display address counter generates the addresses for read out of the display data.
7.9 Command decoder
The command decoder identifies command words that arrive on the I2C-bus and
determines the destination for the following data bytes.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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