PDSP16488A/A0/GC View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16488A/A0/GC' PDF : 33 Pages View PDF
PDSP16488A
8-BIT
PIXEL
DATA
SYNC
PIXEL CLOCK CLK
RESET RES
SYNC
ODD FIELD
PIXEL CLOCK
RESET
CLK
RES
FIELD
DELAY
EPROM
MSB
VDD
GND
15k
NOM
IP7:0
PROG
PC0
CE
GND R/W PDSP16488A RES
834
HRES WINDOW
VDD BYPASS
DELOP
L7:0
D15:0
VDD
15k
NOM
DELAYED
SYNC
PROG
IP7:0
CE
PC1 PDSP16488A RES
834
HRES WINDOW D15:0
GND R/W
BIN
GND BYPASS
OVR
O/C L7:0
OEN
Non-interlaced
DATA OUT
BIN
OVERFLOW
OUTPUT
ENABLE
R/W HOST CPU
REPLY
ADDRESS
DECODE
O/C
PROG
IP7:0
R/W PDSP16488A
834
HRES WINDOW
BYPASS
CE
RES
DELOP
O/C L7:0
D15:0
DELAYED
SYNC
8-BIT
PIXEL
DATA
DS
PROG
PC1
CE
IP7:0 PDSP16488A RES
834
HRES WINDOW D15:0
R/W
BIN
VDD BYPASS
OVR
O/C L7:0
OEN
READ REGISTERS
(TRISTATE ENABLE)
D7:0
DATA OUT
BIN
OVERFLOW
OUTPUT
ENABLE
Interlaced
Fig. 14 8-bit dual device systems
24
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