PDSP16488A/A0/GC View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16488A/A0/GC' PDF : 33 Pages View PDF
16-BIT
PIXEL
DATA
SYNC
PIXEL CLOCK
CLK
RESET
RES
SYNC
ODD FIELD
PIXEL CLOCK
CLK
RESET
RES
EPROM
MSB
VDD
GND
15k
NOM
IP7:0
PROG
PC0
CE
GND R/W PDSP16488A RES
834
HRES WINDOW
VDD BYPASS
DELOP
O/C L7:0
D15:0
VDD
15k
NOM
DELAYED
SYNC
PDSP16488A
MSB
IP7:0
PC1
HRES
PDSP16488A
834
WINDOW
GND R/W
GND BYPASS
O/C L7:0
PROG
CE
RES
D15:0
BIN
OVR
OEN
Non-interlaced
DATA OUT
BIN
OVERFLOW
OUTPUT
ENABLE
R/W HOST CPU
REPLY
ADDRESS
DECODE
O/C
LSB
IP7:0
PROG
CE
R/W PDSP16488A RES
834
HRES WINDOW
BYPASS
DELOP
L7:0
D15:0
LSB
DELAYED
SYNC
16-BIT
PIXEL
DATA
FIELD
DELAY
MSB
VDD
MSB
DS
PC1
IP7:0 PDSP16488A
834
HRES WINDOW
R/W
BYPASS
L7:0
PROG
CE
RES
D15:0
BIN
OVR
OEN
Interlaced
READ REGISTERS
(TRISTATE ENABLE)
D7:0
DATA OUT
BIN
OVERFLOW
OUTPUT
ENABLE
Fig. 15 Dual device 16-bit systems.
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