PDSP16488A/A0/GC View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16488A/A0/GC' PDF : 33 Pages View PDF
PDSP16488A
VDD
EPROM
15k
NOM
UPPER
ADDR BITS
ALS138
PIXEL DATA
PIXEL CLOCK
SYNC
RESET
CLK
HRES
RES
CE2 CE3 CE4
GND
VDD
15k
NOM
GND
VDD
IP7:0
DS
MASTER
PDSP16488A
R/W
(1)
HRES
BYPASS
PC1
PROG
RES
CE O/C
IP7:0
PC0
PC1
DS
PROG
PDSP16488A
GND R/W
(2)
CE CE2
HRES
RES
VDD BYPASS
DELOP
FIELD
DELAY
IP7:0
PC0
PC1
DS
GND R/W
PDSP16488A PROG
(3)
CE CE3
HRES
RES
ODD FIELD
BYPASS
IP7:0
BIN
PC0
PC1
DS
GND R/W
PROG
PDSP16488A
(4)
CE
CE4
HRES
RES
BYPASS
OVR
OEN
DELAYED SYNC
DATA OUT
BIN
OVERFLOW
OUTPUT ENABLE
Fig. 17 Four device interlaced system.
27
Share Link: 
