PDSP16488A/A0/GC View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16488A/A0/GC' PDF : 33 Pages View PDF
PDSP16488A
PIXEL CLOCK
SYNC
RESET
PIXEL
DATA
CLK
HRES
RES
EPROM
DECODE
CE2 CE3 CE4 CE5 CE6 CE7 CE8 CE9
VDD
15k
NOM
VDD
15k
NOM
PROG
DS
O/C
IP7:0
IP7:0
IP7:0
CS3
PC1
PC0
PC1
DS
GND R/W
MASTER
PC1
PDSP16488A
(1)
PROG
PC0
PROG
DS
PROG
PDSP16488A
PDSP16488A
DS
(2)
CE CE2 GND R/W
(3)
CE CE3
HRES
CE O/C GND R/W
RES
HRES
RES
VDD BYPASS
RES
HRES
VDD BYPASS
L7:0
VDD BYPASS
4 CLK
DELAYS
IP7:0
IP7:0
IP7:0
PC1
PC0
PC1
PC0
PC1
DS
PDSP16488A PROG
DS
PDSP16488A PROG
DS
PDSP16488A PROG
GND R/W
(4)
CE CE4 GND R/W
(5)
CE
CE5 GND R/W
(6)
CE
CE6
HRES
RES
HRES
RES
HRES
RES
GND BYPASS
GND BYPASS
GND BYPASS
L7:0
4 CLK
DELAYS
IP7:0
IP7:0
IP7:0
PC1
PC0
PC1
PC0
PC1
DS
PDSP16488A PROG
DS
PDSP16488A PROG
DS
PDSP16488A PROG
GND R/W
(7)
CE CE7 GND R/W
(8)
CE
CE8 GND R/W
(9)
CE
CE9
HRES
RES
HRES
RES
HRES
RES
GND BYPASS
GND BYPASS
GND BYPASS
OVR
O/C L7:0
OEN
DATA
OUT
BIN
OVERFLOW
OUTPUT
ENABLE
DELAYED
SYNC
Fig. 20 Nine device non-interlaced system
30
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