PDSP16488A/A0/GC View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16488A/A0/GC' PDF : 33 Pages View PDF
PDSP16488A
HOST CPU REPLY
ADDRESS
DECODE
PIXEL DATA
PIXEL CLOCK
SYNC
RESET
PROG CE1 CE2 CE3 CE4
CLK
HRES
RES
O/C
IP7:0
DS
PC1
R/W
MASTER PROG
PDSP16488A
HRES
(1)
CE CE1
VDD BYPASS
RES
L7:0
IP7:0
PC0
PC1
DS
PROG
PDSP16488A
R/W
(2)
CE CE2
HRES
RES
VDD BYPASS
DELOP
L7:0
DELAYED SYNC
IP7:0
PC0
PC1
DS
PDSP16488A PROG
R/W
(3)
CE CE3
HRES
RES
GND BYPASS
L7:0
IP7:0
BIN
PC0
PC1
DS
R/W
PROG
PDSP16488A
(4)
CE
CE4
HRES
RES
GND BYPASS
OVR
L7:0
OEN
DATA OUT
BIN
OVERFLOW
OUTPUT ENABLE
Fig. 16 Four device non-interlaced system.
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