PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
5. Posted write transactions must be given opportunities to pass delayed read and write requests and completions.
Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do
not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between
the posted write queue and the delayed transaction queue.
6.4 Data Synchronization
Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus
Specification, Revision 2.1, provides the following alternative methods for synchronizing data and interrupts:
• The device signaling the interrupt performs a read of the data just written (software).
• The device driver performs a read operation to any register in the interrupting device before accessing data
written by the device (software).
• System hardware guarantees that write buffers are flushed before interrupts are forwarded.
PI7C7100 does not have a hardware mechanism to guarantee data synchronization for posted write transactions.
Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just
written (or some other location along the same path), or from the device driver to one of the device registers.
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09/18/00 Rev 1.1
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