PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
Table 7–2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary
interface. This bit is set when PI7C7100 detects a parity error on the secondary interface.
Table 7–2. Setting Secondary Interface Detected Parity Error Bit
Secondary detected
parity error bit
Transaction
Type
Direction
Bus where error
was detected
Primary/Secondary
parity error response bits
0
Read
Downstream
Primary
x/x1
1
Read
Downstream
Secondary
x/x
0
Read
Upstream
Primary
x/x
0
Read
Upstream
Secondary
x/x
0
Posted write
Downstream
Primary
x/x
0
Posted write
Downstream
Secondary
x/x
0
Posted write
Upstream
Primary
x/x
1
Posted write
Upstream
Secondary
x/x
0
Delayed write
Downstream
Primary
x/x
0
Delayed write
Downstream
Secondary
x/x
0
Delayed write
Upstream
Primary
x/x
1
Delayed write
Upstream
Secondary
x/x
Table 7–3 shows setting data parity detected bit in the primary interface’s status register. This bit is set under the following
conditions:
• PI7C7100 must be a master on the primary bus.
• The parity error response bit in the command register, corresponding to the primary interface, must be set.
• The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
Primary data
parity bit
0
0
1
0
0
0
1
0
0
0
1
0
1x =don’t care
Table 7–3. Setting Primary Interface Data Parity Detected Bit
Transaction
Type
Direction
Bus where error was
detected
Primary/Secondary
parity error response bits
Read
Downstream
Primary
x/x1
Read
Downstream
Secondary
x/x
Read
Upstream
Primary
1/x
Read
Upstream
Secondary
x/x
Posted write
Downstream
Primary
x/x
Posted write
Downstream
Secondary
x/x
Posted write
Upstream
Primary
1/x
Posted write
Upstream
Secondary
x/x
Delayed write
Downstream
Primary
x/x
Delayed write
Downstream
Secondary
x/x
Delayed write
Upstream
Primary
1/x
Delayed write
Upstream
Secondary
x/x
40
09/18/00 Rev 1.1
Share Link: 
