PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
Table 7–4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the
following conditions:
• The PI7C7100 must be a master on the secondary bus.
• The parity error response bit must be set in the bridge control register of secondary interface.
• The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Secondary data
parity detected bit
0
1
0
0
0
1
0
0
0
1
0
0
1x =don’t care
Table 7–4. Setting Secondary Interface Data Parity Detected Bit
Transaction
Type
Read
Direction
Downstream
Bus where error was
detected
Primary
Primary/Secondary
parity error response bits
x/x1
Read
Downstream
Secondary
x/1
Read
Upstream
Primary
x/x
Read
Upstream
Secondary
x/x
Posted write
Downstream
Primary
x/x
Posted write
Downstream
Secondary
x/1
Posted write
Upstream
Primary
x/x
Posted write
Upstream
Secondary
x/x
Delayed write Downstream
Primary
x/x
Delayed write Downstream
Secondary
x/1
Delayed write
Upstream
Primary
x/x
Delayed write
Upstream
Secondary
x/x
41
09/18/00 Rev 1.1
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