PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
Because the data has already been delivered with no errors, there is no other way to signal this information back to the
initiator.
If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will not be asserted.
7.3 Data Parity Error Reporting Summary
In the previous sections, the responses of PI7C7100 to data parity errors are presented according to the type of transaction
in progress. This section organizes the responses of PI7C7100 to data parity errors according to the status bits that
PI7C7100 sets and the signals that it asserts.
Table 7–1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This
bit is set when PI7C7100 detects a parity error on the primary interface.
Table 7–1 Setting the Primary Interface Detected Parity Error Bit
Primary detected
parity error bit
Transaction
Type
0
Read
Direction
Downstream
Bus where error
was detected
Primary
Primary/Secondary
parity error response bits
x/x1
0
Read
Downstream
Secondary
x/x
1
Read
Upstream
Primary
x/x
0
Read
Upstream
Secondary
x/x
1
Posted write
Downstream
Primary
x/x
0
Posted write
Downstream
Secondary
x/x
0
Posted write
Upstream
Primary
x/x
0
Posted write
Upstream
Secondary
x/x
1
Delayed write
Downstream
Primary
x/x
0
Delayed write
Downstream
Secondary
x/x
0
Delayed write
Upstream
Primary
x/x
0
Delayed write
Upstream
Secondary
x/x
1x =don’t care
39
09/18/00 Rev 1.1
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