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QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation

Part Name
Description
MFG CO.
'QL5064-33APB484I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
20.0 AC Characteristics at Vcc = 3.3V, TA=25° C (K=1.00)
The AC Specifications, Logic Cell diagrams and waveforms are provided below. To calculate delays,
multiply the appropriate K factor in the “Operating Range” section by the following numbers.
Programmable
Logic Cell
F1
5 Independent
Functions
(Optimized
for Synthesis)
OR
Single Large
Function
Figure 12: QuickPCI Logic Cell Configuration
Symbol
Parameter
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay b
Setup Time b
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
Table 2: Logic Cells
Propagation Delays (ns)Fanout a
1
2
3
4
8
1.4
1.7
2.0
2.3
3.5
1.8
1.8
1.8
1.8
1.8
0.0
0.0
0.0
0.0
0.0
0.8
1.1
1.4
1.7
2.9
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.4
1.7
2.0
2.3
3.5
1.2
1.5
1.8
2.1
3.3
1.9
1.9
1.9
1.9
1.9
1.8
1.8
1.8
1.8
1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25×C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
b. These limits are derived from a representative selection of the slowest paths through the Quick-
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
QL5064 QuickPCI Data Sheet Rev D
••
21
••
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