QL5064 QuickPCI Data Sheet
22.0 QL5064 Pin Type Descriptions
The QL5064 Device Pins are indicated in the table below. These are pins on the device, some of which
connect to the PCI bus, and others that are programmable as user I/O.
Type
IN
OUT
T/S
S/T/S
O/D
Table 16: Pin Type Descriptions
Description
Input. A standard input-only signal
Totem pole output. A standard active output driver
Tri-state. A bi-directional, tri-state input/output pin
Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven high for
at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the PCI system central
resource to sustain the inactive state once the active driver has released the signal.
Open Drain. Allows multiple devices to share this pin as a wired-or.
NOTE: Signal names which end with the character ‘N’ should be considered active-low
(for example, Mst_IRDYN).
Pin/Bus
Name
VCC
VCCIO
GND
T/GND
I/O
I/GCLK
I/ACLK
TDI
TDO
TCL
TMS
TRSTB
STM
FLOAT
Table 17: Pin / Bus Names and Functions
Type
Function
IN
IN
IN
IN
T/S
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
Supply pin. Tie to 3.3V supply.
Supply pin for I/O. Set to 3.3V for 3.3V I/O, 5V for 5.0V compliant I/O
Ground pin. Tie to GND on the PCB.
Thermal Ground. Used to dissipate heat from the device. Tie to GND on
the PCB.
Programmable Input/Output/Tri-State/Bi-directional Pin.
Programmable Input-Only or Global Clock Pin. Tie to VCC or GND if unused.
Programmable Input-Only or Array Clock Pin. Tie to VCC or GND if unused.
JTAG Data In. Tie to VCC if unused.
JTAG Data Out. Leave unconnected if unused.
JTAG Clock. Tie to GND if unused.
JTAG Test Mode Select. Tie to VCC if unused.
JTAG Reset. Tie to GND if unused.
QuickLogic Reserved pin. Tie to GND on the PCB.
Test Data Out pin for QuickLogic use only. Must be isolated and floating at
all times
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