QL5064 QuickPCI Data Sheet
Symbol
TSWA
THWA
TSWD
THWD
TSWE
THWE
TWCRD
Table 3: RAM Cell Synchronous Write Timing
Parameter
Propagation Delays (ns)Fanout
1
2
3
4
8
WA Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
WA Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
WD Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
WD Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
WE Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
WE Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
WCLK to RD (WA=RA) [a]
5.0
5.3
5.6
5.9
7.1
Symbol
TSRA
THRA
TSRE
THRE
TRCRD
Table 4: RAM Cell Synchronous Read Timing
Parameter
Propagation Delays (ns)Fanout a
1
2
3
4
8
RA Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
RA Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
RE Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
RE Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
RCLK to RD [b]
4.0
4.3
4.6
4.9
6.1
Table 5: RAM Cell Asynchronous Read T iming
Symbol
Parameter
Propagation Delays (ns)Fanout
1
2
3
4
8
RPDRD
RA to RD [b]
3.0
3.3
3.6
3.9
5.1
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