QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-33APB484I
QuickLogic Corporation
'QL5064-33APB484I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
Table 6: Input-Only Cells
Symbol
Parameter
Propagation Delays (ns)Fanout b
1 2 3 4 8 12 24
TIN High Drive Input Delay
1.5 1.6 1.8 1.9 2.4 2.9 4.4
TINI High Drive Input, Inverting Delay
1.6 1.7 1.9 2.0 2.5 3.0 4.5
TISU Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1 3.1
TIH Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
TlCLK Input Register Clock To Q
0.7 0.8 1.0 1.1 1.6 2.1 3.6
TlRST Input Register Reset Delay
0.6 0.7 0.9 1.0 1.5 2.0 3.5
TlESU Input Register Clock Enable Setup Time
2.3 2.3 2.3 2.3 2.3 2.3 2.3
TlEH Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
Symbols
tACK
tGCKP
tGCKB
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Table 7: Clock Cells
Propagation Delays (ns)
Loads per Half Column [a]
1 2 3 4 8 10 12 14 16 18 20
1.2 1.2 1.3 1.3 1.5 .16 1.7 1.8 1.9 2 2.1
0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7
0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7
a. The array distributed networks consist of 40 half columns and the global distributed networks consist
of 44 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up
to 11 loads per half column.
Table 8: I/O Cell Input Delays
Symbol
Parameter
Propagation Delays (ns)Fanout [4]
1
2
3
4
8 10
tI/O Input Delay (bidirectional pad)
1.3 1.6 1.8 2.1 3.1 3.6
TISU Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1
TIH Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
TlOCLK Input Register Clock To Q
0.7 1.0 1.2 1.5 2.5 3.0
TlORST Input Register Reset Delay
0.6 0.9 1.1 1.4 2.4 2.9
TlESU Input Register clock Enable Set-Up Time
2.3 2.3 2.3 2.3 2.3 2.3
TlEH Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
QL5064 QuickPCI Data Sheet Rev D
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