QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-33APB484I
QuickLogic Corporation
'QL5064-33APB484I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
23.0 QL5064 External Device Pins
Pin/Bus Name
AD[63:0]
CBEN[7:0]
PAR
PAR64
FRAMEN
REQ64N
DEVSELN
ACK64N
CLK
RSTN
REQN
GNTN
PERRN
SERRN
IDSEL
IRDYN
TRDYN
STOPN
INTAN
Table 18: QL5064 External Device Pins
Type
Function
T/S
PCI Address and Data: 32 bit multiplexed address/data bus.
T/S
PCI Bus Command and Byte Enables: Multiplexed bus which contains byte enables for
AD[31:0] or the Bus Command during the address phase of a PCI transaction.
PCI Parity: Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after
T/S
address or data phases. Master drives PAR on address cycles and PCI writes. The
Target drives PAR on PCI reads.
T/S
PCI Parity Upper DWORD: Even Parity across AD[63:32] and C/BEN[7:4] busses.
S/T/S
PCI Cycle Frame: Driven active by current PCI Master during a PCI transaction. Driven
low to indicate the address cycle, driven high at the end of the transaction.
S/T/S
PCI Request 64-bit transfer: Driven by the PCI Master to request a 64-bit transfer.
Same signal timing as FRAMEN.
S/T/S
PCI Device Select. Driven by a Target that has decoded a valid base address.
S/T/S
PCI Acknowledge 64-bit Transfer: Driven by a Target which has decoded a valid base
address for a 64-bit data transfer. Same timing as DEVSELN.
IN
PCI System Clock Input.
IN
PCI System Reset Input
T/S
PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) wishes to use the
bus. A point to point signal between the PCI Device and the System Arbiter.
PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access to the PCI
IN
bus by the Arbiter. A point to point signal between the PCI device and the System
Arbiter.
S/T/S
PCI Data Parity Error. Driven active by the initiator or target two clock cycles after a data
parity error is detected on the AD and C/BEN busses.
O/D
PCI System Error: Driven active when an address cycle parity error, data parity error
during a special cycle, or other catastrophic error is detected.
IN
PCI Initialization Device Select. Use to select a specific PCI Agent during System
Initialization.
S/T/S
PCI Initiator Ready. Indicates the Initiator’s ability to complete a read or write
transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN
are active.
S/T/S
PCI Target Ready. Indicates the Target’s ability to complete a read or write transaction.
Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active.
S/T/S
PCI Stop. Used by a PCI Target to end a burst transaction.
O/D
Interrupt A. Asynchronous Active-Low Interrupt Request.
QL5064 QuickPCI Data Sheet Rev D
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