QL5332 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332
QuickLogic Corporation
'QL5332' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
Figure 3: RAM Module
RAM Module
MODE[1:0]
W A[a:0]
W D[w:0]
ASYNCRD
RA[a:0]
RD[w:0]
WE
W CLK
RE
RCLK
Mode
64x18
128x9
256x4
512x2
Table 4: RAM Configurations
Address Buses [a:0] Data Buses [w:0]
[5:0]
[17:0]
[6:0]
[8:0]
[7:0]
[3:0]
[8:0]
[1:0]
The RAM modules are dual-ported, with completely independent READ and WRITE ports and separate READ
and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE
ports support synchronous operation. Each port has 18 data lines and 9 address lines, allowing word lengths
of up to 18 bits and address spaces of up to 512 words. Depending on the mode selected, however, some
higher order data or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts
as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for
asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by
connecting corresponding address lines together and dividing the words between modules. This approach
allows up to 512-deep configurations as large as 24 bits wide in the QL5332 device.
A similar technique can be used to create depths greater than 512 words. In this case address signals higher
than the eighth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data
outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
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