QL5332 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332
QuickLogic Corporation
'QL5332' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
Table 2: QL5332 PCI32N Target Interface Signals (Continued)
Signal
Type
Description
Cfg_Write
Usr_Read
Cfg_Read
This signal is active throughout a “configuration write” transaction. The write strobe
O
for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration
write transaction should be generated by logically ANDing this signal with
Usr_Adr_Inc.
O
This signal is active throughout a “user read” transaction, which has been decoded
by Usr_RdDecode at the beginning of the transaction.
O This signal is active throughout a “configuration read” transaction.
Cfg_RdData[31:0]
Usr_RdData[31:0]
I
Data from the PCI configuration registers, required to be presented during PCI
configuration reads.
I Data from the backend, required to be presented during user reads.
Cfg_CmdReg3
Cfg_CmdReg4
Cfg_CmdReg6
Cfg_CmdReg8
Cfg_LatCnt[7:0]
Bits 3 from the Command Register in the PCI configuration space (offset 04h).
I Enable Special Cycle monitoring. If high, the core reports data parity error in Special
Cycles through SERRN if Cfg_CmdReg8 is active.
Bits 4 from the Command Register in the PCI configuration space (offset 04h).
Memory Write and Invalidate (MWI) Enable. If high, the core can generate MWI
I transactions as requested by the backend. Otherwise it uses Memory Write instead
even if MWI is requested. Note that there are also other conditions that limit whether
MWI can be generated by the core.
Bits 6 from the Command Register in the PCI configuration space (offset 04h). Parity
I Error Response. If high, the core uses PERRN to report data parity errors.
Otherwise the core always tristates PERRN.
Bits 8 from the Command Register in the PCI configuration space (offset 04h).
I SERRN Enable. If high, the core uses SERRN to report address parity errors if
Cfg_CmdReg6 is high. Otherwise the core always tristates SERRN.
I 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch).
Cfg_CacheLineSize[7:2]
Usr_MstRdAd_Sel
Upper 6 bits of the Cache Line Size register in the configuration space (offset 0Ch).
I The core always assumes that the lower two bits ([1:0]) of the Cache Line Size
register to be “00”.
Used when a target read operation should return the value set on Mst_RdAd[31:0]
I
instead of Usr_RdData[31:0]. This select pin saves on logic which would otherwise
need to be used to multiplex Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When
this signal is asserted, the data on Usr_RdData[31:0] is ignored.
Usr_MstWrAd_Sel
Cfg_PERR_Det
Cfg_SERR_Sig
Cfg_MstPERR_Det
Usr_TRDY
Used when a target read operation should return the value set on Mst_WrAd[31:0]
I
instead of Usr_RdData[31:0]. This select pin saves on logic which would otherwise
need to be used to multiplex Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When
this signal is asserted, the data on Usr_RdData[31:0] is ignored.
O
Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status
Register must be set in the PCI configuration space (offset 04h).
System error asserted on the PCI bus. When this signal is active, the Signaled
O System Error bit, bit 14 of the Status Register, must be set in the PCI configuration
space (offset 04h).
O
Data parity error detected on the PCI bus by the master. When this signal is active,
bit 8 of the Status Register must be set in the PCI configuration space (offset 04h).
O
Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only
within target accesses to the core.
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