QL5332 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332
QuickLogic Corporation
'QL5332' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
Signal
Mst_BE_Sel
Mst_WrBurst_Done
Mst_Rd_Term_Sel
Mst_One_Read
Mst_Two_Reads
Mst_RdData_Valid
Mst_RdBurst_Done
Flush_FIFO
Mst_LatCntEn
Mst_Xfer_D1
Mst_Last_Cycle
Mst_REQN
Mst_IRDYN
Mst_Tabort_Det
Mst_TTO_Det
Table 1: QL5332 PCI32N Master Interface Signals (Continued)
Type
Description
Byte enable select for master transactions. When low, Mst_BE[3:0] should remain
unchanged throughout the entire transfer (when Mst_Burst_Req is active) and it is used
I for every data phase of the master transaction. When high, Mst_BE[3:0] pushed into
internal FIFO using Mst_WrData_Valid (along with data in case of a master write) is
used. Should be held unchanged throughout the transaction.
O Requested master write transaction is completed. Active for only one clock cycle.
Master read termination mode select when Mst_BE_Sel is high. When both
Mst_BE_Sel and Mst_Rd_Term_Sel are high, master read termination happens when
I
the internal FIFO is empty (out of byte enables). Mst_Two_Reads and Mst_One_Read
(from backend) are ignored in this case. When either Mst_BE_Sel or Mst_Rd_Term_Sel
is low, Mst_Two_Reads and Mst_One_Read are used to signal end of master read.
Should be held unchanged throughout the transaction.
This signals to the core that only one data transfer remains to be read in the burst read.
I
Should be asserted after the backend receives the second last piece of data from the
core. In the case of a single-data-phase master read request, it should be asserted at
the time it makes the request.
This signals to the core that only two data transfers remain to be read in the burst read.
I Should be asserted after the backend receives the third last piece of data from the core.
It has no effect on single-data-phase master read requests.
Master read data valid on Usr_Addr_WrData[31:0] from the core to the backend. This
O serves as the PUSH control for the external FIFO in the backend that receives data from
the core.
O Requested master read transaction is completed. Active for only one clock cycle.
I
Internal FIFO flush. The internal FIFO is flushed immediately after it is sampled active
on the rising edge of a PCI clock. Not usually used.
I
Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration
space (offset 0Ch). For full PCI compliance, this port should be always set to 1.
Data was transferred on the PCI bus in the previous clock cycle in PCI32_25N-initiated
O master transactions. Useful for updating DMA transfer counts on DMA Read operations
and for updating master write address on DMA Write operations.
O Active during the last data transfer of a master transaction.
O
Copy of the PCI REQN signal generated by QL5332 as a PCI master. Not usually used
in the backend design.
O
Copy of the PCI IRDYN signal generated by QL5332 as a PCI master. Valid only when
QL5332 is the PCI master. Kept high otherwise. Not usually used in the backend design.
O
Target abort detected during master transaction. This is normally an error condition to
be handled in the DMA controller.
O
Target timeout detected (master abort, no response from target). This is normally an
error condition to be handled in the DMA controller.
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