QL5332 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332
QuickLogic Corporation
'QL5332' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
Signal
Usr_STOP
Usr_DEVSEL
Usr_Last_Cycle_D1
Usr_Rdy
Usr_Stop
Usr_Abort
Table 2: QL5332 PCI32N Target Interface Signals (Continued)
Type
Description
O
Inverted copy of the STOPN signal as driven by the PCI target interface. Valid only
within target accesses to the core.
O
Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid
only within target accesses to the core.
O
Active one clock cycle after the last data phase occurs on PCI. Active only for one
clock cycle.
Used to delay (add wait states to) a target PCI transaction when the backend needs
I additional time to provide data (read) or accept data (write). Subject to PCI latency
restrictions if PCI compliance is needed.
I Used to prematurely stop a PCI target access.
I
Used to signal Target Abort on PCI when the backend is unable to complete a
transaction and does not want the master to retry. Rarely used.
Internal PCI Signals
The internal PCI signals for QL5332 PCI32N are shown in Table 3.
Signal
PCI_clock
PCI_reset
PCI_IRDYN_D1
PCI_FRAMEN_D1
PCI_DEVSELN_D1
PCI_TRDYN_D1
PCI_STOPN_D1
PCI_IDSEL_D1
PCI_GNTN_D1
Table 3: QL5332 PCI32N Internal PCI Signals
Type
Description
O PCI clock. On a global clock network.
Inverted and synchronized PCI reset signal. Active high. When the PCI reset is
O removed, this signal also goes from high to low but synchronized to the PCI clock.
On a global clock network.
O Copy of the IRDYN signal from the PCI bus, delayed by one clock.
O Copy of the FRAMEN signal from the PCI bus, delayed by one clock.
O Copy of the DEVSELN signal from the PCI bus, delayed by one clock.
O Copy of the TRDYN signal from the PCI bus, delayed by one clock.
O Copy of the STOPN signal from the PCI bus, delayed by one clock.
O Copy of the IDSEL signal from the PCI bus, delayed by one clock.
O Copy of the GNTN signal from the PCI bus, delayed by one clock.
RAM Module Features
The QL5332 device has twelve 1,152-bit RAM modules, for a total of 13,824 RAM bits. Using two “mode”
pins, designers can configure each module into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 blocks (see
Figure 3). The blocks are also easily cascadable to increase their effective width or depth. See Table 4 for
RAM mode configurations.
© 2004 QuickLogic Corporation
www.quicklogic.com
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