QL5332 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332
QuickLogic Corporation
'QL5332' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
Target Interface Signals
The target interface signals for QL5332 PCI32N are shown in Table 2.
Table 2: QL5332 PCI32N Target Interface Signals
Signal
Usr_Addr_WrData[31:0]
Usr_CBE[3:0]
Usr_Adr_Valid
Usr_Adr_Inc
Usr_RdDecode
Usr_WrDecode
Usr_Select
Usr_Write
Type
Description
Target address and target write data. During all target accesses, the address is
presented on Usr_Addr_WrData[31:0] at the same time Usr_Adr_Valid is active.
O
During target write transactions, this port also presents valid write data to the PCI
configuration space or user logic when Usr_Adr_Inc is active. During master read
transactions, this port also presents valid data read from PCI to the backend. This is
the registered version of the PCI AD[31:0] signal.
PCI command and byte enables. During target accesses, the PCI command is
O
presented on Usr_CBE[3:0] at the same time Usr_Adr_Valid is active. This port also
presents active-low byte enables to the PCI configuration space or user logic. This
is the registered version of the PCI CBEN[3:0] signal.
Indicates the beginning of a PCI transaction, and that a target address is valid on
Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this
signal is active, the target address must be latched and decoded to determine if this
O address belongs to the device memory or I/O space. Also, the PCI command must
be decoded to determine the type of PCI transaction. On subsequent clocks of a
target access, this signal is low, indicating that the address is no longer on
Usr_Addr_WrData[31:0].
This signal, when asserted, indicates that the target address should be
incremented, because the previous data transfer has completed. During burst target
accesses, the target address is only presented to the backend at the beginning of
the transaction when Usr_Adr_Valid is active, and must therefore be latched and
O incremented (by 4) for subsequent data transfers. For target write transactions,
Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that must be accepted
by the backend logic (regardless of the state of Usr_Rdy). For read transactions,
Usr_Adr_Inc signals to the backend that the core has presented the read data onto
the PCI bus (has asserted TRDYN).
This signal must be asserted by the backend when a user read command (e.g.,
I
Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc.) has been
decoded from Usr_CBE[3:0]. It is acknowledged by the core only when
Usr_Adr_Valid is active.
This signal must be asserted by the backend when a user write command (e.g.,
I Memory Write, Memory Write and Invalidate, I/O Write, etc.) has been decoded from
Usr_CBE[3:0]. It is acknowledged by the core only when Usr_Adr_Valid is active.
This signal must be driven active when the address on Usr_Addr_WrData[31:0] has
been decoded and determined to be within the address space of the device.
Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address
I Registers in the PCI configuration space. Also, this signal must be gated by the
Memory Access Enable or I/O Access Enable registers in the PCI configuration
space (Command Register bits 1 or 0 at offset 04h). This signal is acknowledged by
the core only when Usr_Adr_Valid is active.
This signal is active throughout a “user write” transaction, which has been decoded
O
by Usr_WrDecode at the beginning of the transaction. The write strobe for individual
DWORDs of data (on Usr_Addr_WrData[31:0]) during a user write transaction
should be generated by logically ANDing this signal with Usr_Adr_Inc.
© 2004 QuickLogic Corporation
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