SAA7392HL/M2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HL/M2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.5.3 PLL LOCK SELECT REGISTER (PLLLOCK)
The behaviour of this register is dependent upon whether its being read or written. The behaviour for the write operation
is described in Tables 24 to 27. When read the 8 MSBs of the PLL frequency counter are returned; this is described in
Tables 24 and 28.
Table 24 PLL Lock Select Register (address 00H) - WRITE/READ
7
LockOride
PLLFreq.7
6
PhaOset.2
PLLFreq.6
5
PhaOset.1
PLLFreq.5
4
PhaOset.0
PLLFreq.4
3
2
1
0
PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0
PLLFreq.3 PLLFreq.2 PLLFreq.1 PLLFreq.0
Table 25 Description of PLLLock bits for write operation
BIT
SYMBOL
DESCRIPTION
7
LockOride When LockOride = 0, then automatic lock behaviour selected, PLLForceL<3:0> must be
set to ‘0000’. When LockOride = 1, then PLL manual override, PLLForceL<3:0> must
also be programmed.
6
PhaOset.2 These 3 bits are used to select the phase override settings; see Table 26.
5
PhaOset.1
4
PhaOset.0
3
PLLForceL.3 These 4 bits are used to select the PLL lock; see Table 27.
2
PLLForceL.2
1
PLLForceL.1
0
PLLForceL.0
Table 26 Selection of phase override setting
PhaOset.2
0
0
0
0
1
1
1
1
PhaOset.1
0
0
1
1
0
0
1
1
PhaOset.0
0
1
0
1
0
1
0
1
PHASE OVERRIDE
reserved
3/8 × PLL clock over-equalized T3
2/8 × PLL clock over-equalized T3
1/8 × PLL clock over-equalized T3
correct equalisation
1/8 × PLL clock under-equalized T3
2/8 × PLL clock under-equalized T3
3/8 × PLL clock under-equalized T3
Table 27 Selection of PLL lock
PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0
PLL LOCK
0
0
0
0
automatic lock behaviour
0
0
0
1
force PLL in-lock
0
1
0
0
force PLL into outer-lock
0
1
1
0
force PLL into inner-lock
1
0
0
0
force PLL into Hold mode (PLL frequency can be
forced using preset value in register PLLFreq)
X
X
X
X
all other combinations are reserved
2000 Mar 21
22
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