SAA7392HL/M2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HL/M2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
Table 33 Selection of PLL bandwidth
PLLBWF1.1 PLLBWF1.0
0
0
21000 Hz
0
1
10528 Hz
1
0
5264 Hz
1
1
2632 Hz
PLL BANDWIDTH
Table 34 Selection of low-pass bandwidth
LPBWF2.1
0
0
1
1
LPBWF2.0
0
1
0
1
42100 Hz
21000 Hz
10528 Hz
This value is reserved.
LOW-PASS BANDWIDTH
7.5.5 PLL FREQUENCY PRESET REGISTER (PLLFREQ)
The function of this register is dependent upon whether its being read or written. Tables 35 and 36 define the register
function for the write operation. Tables 35 and 37 define the register function for the read operation.
Table 35 PLL Frequency Preset Register (address 02H) - WRITE/READ
7
PLLFreq.9
JV.7
6
PLLFreq.8
JV.6
5
PLLFreq.7
JV.5
4
PLLFreq.6
JV.4
3
PLLFreq.5
JV.3
2
PLLFreq.4
JV.2
1
PLLFreq.3
JV.1
0
PLLFreq.2
JV.0
Table 36 Description of PLLFreq bits for write operation
BIT
7 to 0
SYMBOL
DESCRIPTION
PLLFreq<9:2> These are the 8 MSBs of the 10-bit code used to set the PLL frequency. The 2 LSBs
reside in the PLLEqu register; these 2 bits should be written to first. The PLL frequency
can be set using the following equation:
fPLL
=
P-----L---L---F----5r--e-1--q-2---<---9---:--0--->--
+
2–5
× fclk
Table 37 Description of PLLFreq bits for read operation
BIT
7 to 0
SYMBOL
DESCRIPTION
JV.7 to JV.0 Jitter value. These 8 bits determine the PLL clock jitter value (jitter values below 7%
cannot be measured with this register). The absolute clock jitter value can be calculated
as follows:
PLL clock recovery jitter % = J----V----<---7-2--:--00---4>---8--–-----6---.--5-- × 100
2000 Mar 21
24
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