SAA7392HL/M2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HL/M2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.5.7 PLL LOCK AID2 PRESET REGISTER (PLLFMEAS)
The PLL setting point for the EFM counting locking strategy is controlled by setting the PLL frequency such that, there
are, on average, a fixed number of EFM transitions per PLL clock period:
PLL Locking Frequency/EFM Transition Frequency = (EFM_Count + 32)/16 = 4.75 in a typical application.
This value (4.75) is dependent on disc and mechanical variations, improvements may be achieved by adjusting the value
slightly.
Table 42 PLL Lock Aid2 Preset Register (address 04H) - WRITE
7
RL3_En
6
5
4
3
−
EFMns.5
EFMns.4
EFMns.3
2
EFMns.2
1
EFMns.1
0
EFMns.0
Table 43 Description of PLLFMeas bits
BIT
7
6
5 to 0
SYMBOL
RL3_En
−
EFMns<5:0>
DESCRIPTION
If RL3_En = 0, then EFM transition counting outer PLL lock strategy. If RL3_En = 1,
then RL3 detection PLL outer lock strategy.
This bit is reserved.
These 6 bits select the EFM nominal setting. The default nominal setting should be set
to ‘101110’.
7.5.8 MOTOR CONTROL REGISTER 2 (MOTOR2)
This is a dual-function register. When read Motor2 gives an indication of the EYE opening of the equalised HF.
Table 44 Eye Open Register (address 0DH) - READ
7
EOV.7
6
EOV.6
5
EOV.5
4
EOV.4
3
EOV.3
2
EOV.2
1
EOV.1
0
EOV.0
2000 Mar 21
26
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