SAA7392HL/M2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HL/M2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
Table 28 Description of PLLock bits for read operation
BIT
7 to 0
SYMBOL
DESCRIPTION
PLLFreq<7:0> This register holds the 8 MSBs of the PLL frequency counter. The PLL frequency is
calculated as shown below:
fPLL(Hz) = (---P----L---L----F---r--e----q---<----7---:--0--->---1--×-2----8A----D----C------c---l--o---c---k-----(--H----z---)--)
7.5.4 PLL BANDWIDTH SELECT REGISTER (PLLSET)
The function of this register is dependent upon whether its being read or written. The function for the write operation is
described in Tables 29 to 34. Note the measurement conditions are: system clock = 2.15 MHz, bit clock = 4.3 MHz,
bandwidth is proportional to the system clock.
When read this register returns the 8-bit PLL asymmetry value, see Table 29.
Table 29 PLL Bandwidth Select Register (address 01H) - WRITE/READ
7
SliceBW.1
PLLAsym.7
6
SliceBW.0
PLLAsym.6
5
IntegF0.1
PLLAsym.5
4
IntegF0.0
PLLAsym.4
3
PLLBWF1.1
PLLAsym.3
2
PLLBWF1.0
PLLAsym.2
1
LPBWF2.1
PLLAsym.1
0
LPBWF2.0
PLLAsym.0
Table 30 Description of PLLSet bits for write operation
BIT
SYMBOL
DESCRIPTION
7
SliceBW.1 These 2 bits select the Slicer bandwidth; see Table 31.
6
SliceBW.0
5
IntegF0.1 These 2 bits select the integrator crossover frequency; see Table 32.
4
IntegF0.0
3
PLLBWF1.1 These 2 bits select the PLL bandwidth; see Table 33.
2
PLLBWF1.0
1
LPBWF2.1 These 2 bits select the low-pass bandwidth; see Table 34.
0
LPBWF2.0
Table 31 Selection of Slicer bandwidth
SliceBW.1
0
0
1
1
SliceBW.0
0
1
0
1
12 Hz
50 Hz
200 Hz
This value is reserved.
SLICER BANDWIDTH
Table 32 Selection of integrator crossover frequency
IntegFO.1
0
0
1
1
IntegFO.0
0
1
0
1
INTEGRATOR CROSSOVER FREQUENCY
3780 Hz
1890 Hz
945 Hz
This value is reserved.
2000 Mar 21
23
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