ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
7 Pin description
ST40RA166
Pin name
PIDSEL
NOTPRST
NOTPLOCK
PCLK
NOTPREQ0
NOTPREQ1
BPN
Row Col
Architecture
signal name
Pin function
Default
Alternate
J
16
PCI_IDSEL
PCI initialization device
R
16
NOTPCI_RST
PCI reset
L
20
NOTPLOCK
PCI exclusive access
F
19
PCI_CLK
PCI clock input
E
18
NOTPCI_REQ0
PCI external request for bus PIO16
E
17
NOTPCI_REQ1
PCI external request for bus PIO18
NOTPREQ2
NOTPREQ3
NOTPGNT0
NOTPGNT1
NOTPGNT2
NOTPGNT3
PCLKOUT
NOTPINTA
DACK0
DRAK0
DREQ0
DACK1
DRAK1
DREQ1
SCI2
CTS1
RXD0
RXD1
SCK0
SCK1
TXD0
63/88
F
16
NOTPCI_REQ2
PCI external request for bus PIO20
G
16
NOTPCI_REQ3
PCI external request for bus PIO22
EMPIDREQ1
D
18
NOTPCI_GNT0
PCI grant external request
PIO17
D
17
NOTPCI_GNT1
PCI grant external request
PIO19
E
16
NOTPCI_GNT2
PCI grant external request
PIO21
D
16
NOTPCI_GNT3
PCI grant external request
PIO23
EMPIDRAK1
F
20 PCI_CLOCKOUT PCI clock output
PIO14
T
19
NOTPCI_INTA
PCI interrupt request
PIO15
U
19
DACK0
DMA bus acknowledge
PIO10
EMPIDACK2
U
18
DRACK0
DMA request acknowledge
PIO9
EMPIDRAK2
V
20
DREQ0
DMA transfer request
PIO8
EMPIDREQ2
U
20
DACK1
DMA bus acknowledge
PIO13
EMPIDACK3
T
20
DRACK1
DMA request acknowledge
PIO12
EMPIDRAK3
U
17
DREQ1
DMA transfer request
PIO11
EMPIDREQ3
V
19
RTS1/PIO7
SCI2 transmission request
PIO7
V
18
CTS1/PIO6
SCI2 transmission enabled
PIO6
Y
19
RXD0/PIO1
SCI receive data input
PIO1
W
20
RXD1/PIO4
SCI receive data input
PIO4
Y
18
SCK0/PIO0
SCI clock input
PIO0
W
18
SCK1/PIO3
SCI clock input
PIO3
Y
20
TXD0/PIO2
SCI transmit data output
PIO2
Table 34: PBGA ballout for ST40RA166 (page 6 of 11)
Pin
Type
Dir
-
I/O
P8
I/O
P8
I
P8
I
P8
I/O I/O
P8
I
I/O
P8
I
I/O
P8
I
I/O
O
P8
I/O I/O
P8
O I/O
P8
O I/O
P8
O I/O
I
P8
O I/O
P8
I/O I/O
C2A O I/O
I
C2A O I/O
I
C2A I
I/O
O
C2A O I/O
I
C2A O I/O
I
C2A I
I/O
O
C2A O I/O
C2A O I/O
C2A I
I/O
C2A I
I/O
C2A I
I/O
C2A I
I/O
C2A O I/O
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