ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
7 Pin description
ST40RA166
7.4 Pin states
The following table shows the direction and state of the pins during and immediately after reset.
q Z indicates an output or I/O pin that has been tri-stated.
q I indicates an input or I/O pin in input modes (I/O buffer tri-stated).
q 1 indicates an output or I/O pin driving logical high.
q 0 indicates an output or I/O pin driving logical low.
q X indicates an output or I/O pin driving undefined data.
q H indicates a pin with weak internal pull-up enabled.
q L indicates a pin with weak internal pull-down enabled.
Pin names
LMI system pins
LDATA0:63
LBANK0:1
LADDR0:14
LDQS0:7
LCLKOUTA:B
NOTLCLKOUTA:B
LDQM0:7
NOTLCSA/B0:1,
NOTLRASA:B, NOTLCASA:B,
NOTLWEA:B
LCLKEN0:1
PCI system pins
PAD0:31
NOTPCBE0:3
PPAR
NOTPFRAME
NOT PIRDY
NOTPTRDY
NOTPSTOP
NOTPERR
NOTPSERR
NOTPDEVSEL
PIDSEL
NOTPRST
Architecturally defined
reset state
Implementation reset state during and after
reset
Dir During reset Dir During reset
Following reset
I/O
Z
I/O
Z
O
X
I/O
11
O
X
I/O
1...1
I/O
Z
I/O
Z
O
1
I/O
X
O
0
I/O
X
O
X
I/O
X
O
1
I/O
11
O
1
I/O
1
O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
1
I/O
H
I/O
1
I/O
H
I/O
1
I/O
H
I/O
1
I/O
H
I/O
1
I/O
H
I/O
1
I/O
H
I/O
1
I/O
H
I/O
0
I
0
I/O
0
I/O
0
Table 35: Pin reset states for ST40RA166
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