ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
7 Pin description
ST40RA166
Pin names
Architecturally defined
reset state
Implementation reset state during and after
reset
Dir During reset Dir During reset
Following reset
EMI system pins
EADDR[2:26]A
O
EDATA[0:31]
I/O
ECLKOUT, MCLKOUT, FCLKOUT
O
ECLKEN
O
EDQM[0:3]
O
NOTECS[0:5]
O
NOTERAS, NOTECAS, NOTEWE
I/O
EWAIT
I/O
EPENDING
O
I
NOTMREQ (HLD_ACK when
I
EMI slave)
NOTMACK (HLD_REQ when
O
EMI slave)
NOTFBAA
O
NOTESCS[0:2]
O
Z
Z
0
Z
Z
1
1
Z
0 (MD7 = 0)
Z (MD7 = 1)
-
Z
Z
Z
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
MD7
=0
I
O
O
I/O
ZZZE740
(Mode 0)
Z
Z
Z
Z
Z
Z
Z
0
Z
0
1
1111
111111
1
Z
0
Z
1
1
Z
Table 35: Pin reset states for ST40RA166
a. The reset state of the EADDR bus is tri-state, the value given corresponds to a specific boot mode
and shows the expected ties.
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