ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
A Interconnect architecture
A.1 Arbitration schemes
A.1.1 PCI arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) for fixed priority mode has to be in the following priority order:
q CPU buffer,
q EMPI,
q GPDMA,
q PCI (PCI master request, although not expected, get served to avoid deadlock).
The priority orders have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.2 EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI)
The default configuration (after reset) for fixed priority mode has to be in the following priority order:
q CPU buffer,
q PCI,
q EMPI,
q GPDMA.
The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.3 LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:
q CPU,
q GPDMA and PCI buffer.
The priority orders have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.4 PER arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:
q CPU buffer,
q PCI,
q EMPI,
q GPDMA.
The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
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