ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
A Interconnect architecture
A Interconnect architecture
ST40RA166
This detail is included for information only. It is not recommended to write to any of these registers,
without prior consultation from ST, as it could cause the device to malfunction.
ST only guarantees correct operation of the device with the default register values. The register
reset default values have been programmed to balance the system and give optimum system
performance, so there is no need to modify them.
For details of other registers see the ST40 System Architecture Manual.
The internal architecture of the block is shown in Figure 20.
SH4 subsystem
ST40 core T3
32
Node 1
64-bit
full
T3
cross bar
64 conn_2 x 2
CPU subsystem
T3
64
LMI
PCI
PCI
(t)
100 MHz
GPDMA
EMPI
T3
32
T3
32
T3
32
T3
32
Node 2
32-bit
Full cross bar
T3
32
EMI
subsystem
conn_4 x 4
PI
PER
sub
Proggrrammmiinng
poorrt
Figure 20: ST40RA166 interconnect architecture
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