ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
A Interconnect architecture
Address
offset
Name
Function
0x318
0x320
0x328
0x330
0x410
0x418
0x420
0x428
0x430
PCI_CPU_PRI
PCI_LATENCY_PCI
PCI_LATENCY_EMPI
PCI_LATENCY_GPDMA
LATENCY_PER_ENABLE
PER_CPU_PRI
PER_LATENCY_PCI
PER_LATENCY_EMPI
PER_LATENCY_GPDMA
Defines priority for the CPU in the PCI arbiter, see page 79
Defines priority and latency value for PCI initiator in the PCI arbiter, see page 79
Defines priority and latency value for EMPI initiator in the PCI arbiter, see
page 79
Defines priority and latency value for GPDMA initiator in the PCI arbiter, see
page 80
Enables or disables initiators latency counters, see page 80
Defines priority for the CPU in the peripheral arbiter, see page 80
Defines priority and latency value for PCI initiator in the peripheral arbiter, see
page 80
Defines priority and latency value for EMPI initiator in the peripheral arbiter, see
page 81
Defines priority and latency value for GPDMA initiator in the peripheral arbiter,
see page 81
Table 36: Interconnect register summary
A.2.1 LMI1 arbiter
LATENCY_LMI1_ENABLE
0 Reserved
1 ENABLE_1
[31:2] Reserved
LMI1 arbiter: enable latency counters
Reset: Always 0
Enable latency check for node 2
Reset: 0
Reset: Always 0
0x010
RW
LMI1_CPU_PRI
[3:0] CPU_PRIORITY
[31:4] Reserved
LMI1 arbiter: CPU priority
Defines priority for CPU
Reset: 0x1
0x018
RW
LATENCY_LMI1_VALUE
[3:0] NODE2_PRIORITY
[15:4] Reserved
[23:16] NODE2_LATENCY
[31:24] Reserved
LMI1 arbiter: node 2 intitiator priority and latency
Defines priority for node 2 initiators
Reset: 0x0
Defines maximum accepted latency for node 2 initiators
Reset: 0x00
0x020
RW
RW
76/88
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