ST40RA166 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST40RA166

32-bit Embedded SuperH Device

STMicroelectronics 

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ST40RA166

A Interconnect architecture

PCI_LATENCY_EMPI

[23:16] EMPI_LATENCY

[31:24] Reserved

PCI arbiter: EMPI intitiator priority and latency

Defines maximum accepted latency for EMPI

Reset: 0x00

0x328

RW

PCI_LATENCY_GPDMA

[3:0] GPDMA_PRIORITY

[15:4] Reserved

[23:16] GPDMA_LATENCY

[31:24] Reserved

PCI arbiter: GPDMA intitiator priority and latency

Defines priority for GPDMA

Reset: 0x1

Defines maximum accepted latency for GPDMA

Reset: 0x00

A.2.5 Peripheral arbiter

LATENCY_PER_ENABLE

0 Reserved

1 ENABLE_PCI

2 ENABLE_EMPI

3 ENABLE_GPDMA

[31:4] Reserved

Peripheral arbiter: enable latency counters

Reset: Always 0

Enable latency check for PCI

Reset: 0

Enable latency check for EMPI

Reset: 0

Enable latency check for GPDMA

Reset: 0

Reset: Always 0

0x330

RW

RW

0x410

RW

RW

RW

PER_CPU_PRI

[3:0] CPU_PRIORITY

[31:4] Reserved

Peripheral arbiter: CPU priority

Defines priority for CPU

Reset: 0x3

0x418

RW

PER_LATENCY_PCI

[3:0] PCI_PRIORITY

[15:4] Reserved

[23:16] PCI_LATENCY

[31:24] Reserved

Peripheral arbiter: PCI intitiator priority and latency

Defines priority for PCI

Reset: 0x2

0x420

RW

Defines maximum accepted latency for PCI

RW

Reset: 0x00

80/88

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