ST40RA166 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST40RA166

32-bit Embedded SuperH Device

STMicroelectronics 

Prev 71 72 73 74 75 76 77 78 79 80 Next

ST40RA166

A Interconnect architecture

LMI2_LATENCY_GPDMA

[23:16] GPDMA_LATENCY

[31:24] Reserved

A.2.3 EMI arbiter

LATENCY_EMI_ENABLE

0 Reserved

1 ENABLE_PCI

2 ENABLE_EMPI

3 ENABLE_GPDMA

[31:4] Reserved

LMI2 arbiter: GPDMA intitiator priority and latency

Defines maximum accepted latency for GPDMA

Reset: 0x00

0x130

RW

EMI arbiter: enable latency counters

Reset: Always 0

Enable latency check for PCI

Reset: 0

Enable latency check for EMPI

Reset: 0

Enable latency check for GPDMA

Reset: 0

Reset: Always 0

0x210

RW

RW

RW

EMI_CPU_PRI

[3:0] CPU_PRIORITY

[31:4] Reserved

EMI arbiter: CPU priority

Defines priority for CPU

Reset: 0x3

0x218

RW

EMI_LATENCY_PCI

[3:0] PCI_PRIORITY

[15:4] Reserved

[23:16] PCI_LATENCY

[31:24] Reserved

EMI arbiter: PCI intitiator priority and latency

Defines priority for PCI

Reset: 0x2

Defines maximum accepted latency for PCI

Reset: 0x00

0x220

RW

RW

EMI_LATENCY_EMPI

[3:0] EMPI_PRIORITY

[15:4] Reserved

[23:16] EMPI_LATENCY

[31:24] Reserved

EMI arbiter: EMPI intitiator priority and latency

Defines priority for EMPI

Reset: 0x1

Defines maximum accepted latency for EMPI

Reset: 0x00

0x228

RW

RW

78/88

Share Link: