ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
A Interconnect architecture
ST40RA166
A.1.5 LMI2 arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:
q PCI,
q EMPI,
q GPDMA,
q CPU buffer (although the CPU requests are not supposed to go in that node to be send in the
LMI, it has to be managed in order to avoid deadlock).
The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.6 Return arbitration
The possibilities of the return arbitration are simpler than for the request arbitration. The arbiter is
not programmable but a specific arbitration can be chosen when implementing it.
The arbitration mode chosen is the fixed priority. For each arbiter (one per initiator), the order is the
following: LMI then other targets for the arbiters in node 1 and LMI, EMI, PCI, peripheral subsystem
for the arbiters of node 2.
A.2 Interconnect registers
A summary of registers is given in Table 36. Addresses in the table are offset from the interconnect
base address at 0x1B05 0000.
Address
offset
Name
Function
0x010
0x018
0x020
0x110
0x118
0x120
0x128
LATENCY_LMI1_ENABLE
LMI1_CPU_PRI
LATENCY_LMI1_VALUE
LATENCY_LMI2_ENABLE
LMI2_CPU_PRI
LMI2_LATENCY_PCI
LMI2_LATENCY_EMPI
Enables or disables initiators latency counters, see page 76
Defines priority for the CPU in the LMI1 arbiter, see page 76
Defines priority and latency value for the node 2 in the LMI1 arbiter, see page 76
Enables or disables initiators latency counters, see page 77
Defines priority for the CPU in the LMI2 arbiter, see page 77
Defines priority and latency value for PCI initiator in the PCI arbiter, see page 77
Defines priority and latency value for EMPI initiator in the PCI arbiter, see
page 77
0x130
0x210
0x218
0x220
0x228
LMI2_LATENCY_GPDMA
LATENCY_EMI_ENABLE
EMI_CPU_PRI
EMI_LATENCY_PCI
EMI_LATENCY_EMPI
Defines priority and latency value for GPDMA initiator in the PCI arbiter, see
page 77
Enables or disables initiators latency counters, see page 78
Defines priority for the CPU in the EMI arbiter, see page 78
Defines priority and latency value for PCI initiator in the EMI arbiter, see page 78
Defines priority and latency value for EMPI initiator in the EMI arbiter, see
page 78
0x230
0x310
EMI_LATENCY_GPDMA
LATENCY_PCI_ENABLE
Defines priority and latency value for GPDMA initiator in the EMI arbiter, see
page 79
Enables or disables initiators latency counters, see page 79
Table 36: Interconnect register summary
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