ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
A Interconnect architecture
ST40RA166
EMI_LATENCY_GPDMA
[3:0] GPDMA_PRIORITY
[15:4] Reserved
[23:16] GPDMA_LATENCY
[31:24] Reserved
A.2.4 PCI arbiter
LATENCY_PCI_ENABLE
0 Reserved
1 ENABLE_PCI
2 ENABLE_EMPI
3 ENABLE_GPDMA
[31:4] Reserved
EMI arbiter: GPDMA intitiator priority and latency
Defines priority for GPDMA
Reset: 0x0
Defines maximum accepted latency for GPDMA
Reset: 0x00
0x230
RW
RW
PCI arbiter: enable latency counters
Enable latency check for PCI
Reset: 0
Enable latency check for EMPI
Reset: 0
Enable latency check for GPDMA
Reset: 0
Reset: Always 0
0x310
RW
RW
RW
PCI_CPU_PRI
[3:0] CPU_PRIORITY
[31:4] Reserved
PCI arbiter: CPU priority
Defines priority for CPU
Reset: 0x3
0x318
RW
PCI_LATENCY_PCI
[3:0] PCI_PRIORITY
[15:4] Reserved
[23:16] PCI_LATENCY
[31:24] Reserved
PCI arbiter: PCI intitiator priority and latency
Defines priority for PCI
Reset: 0x0
Defines maximum accepted latency for PCI
Reset: 0x00
0x320
RW
RW
PCI_LATENCY_EMPI
[3:0] EMPI_PRIORITY
[15:4] Reserved
PCI arbiter: EMPI intitiator priority and latency
Defines priority for EMPI
Reset: 0x2
0x328
RW
79/88
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