ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
A Interconnect architecture
A.2.2 LMI2 arbiter
LATENCY_LMI2_ENABLE
0 Reserved
1 ENABLE_PCI
2 ENABLE_EMPI
3 ENABLE_GPDMA
[31:4] Reserved
LMI2 arbiter: enable latency counters
Reset: Always 0
Enable latency check for PCI
Reset: 0
Enable latency check for EMPI
Reset: 0
Enable latency check for GPDMA
Reset: 0
Reset: Always 0
ST40RA166
0x110
RW
RW
RW
LMI2_CPU_PRI
[3:0] CPU_PRIORITY
[31:4] Reserved
LMI2 arbiter: CPU priority
Defines priority for CPU
Reset: 0x0
0x118
RW
LMI2_LATENCY_PCI
[3:0] PCI_PRIORITY
[15:4] Reserved
[23:16] PCI_LATENCY
[31:24] Reserved
LMI2 arbiter: PCI intitiator priority and latency
Defines priority for PCI
Reset: 0x3
Defines maximum accepted latency for PCI
Reset: 0x00
0x120
RW
RW
LMI2_LATENCY_EMPI
[3:0] EMPI_PRIORITY
[15:4] Reserved
[23:16] EMPI_LATENCY
[31:24] Reserved
LMI2 arbiter: EMPI intitiator priority and latency
Defines priority for EMPI
Reset: 0x2
Defines maximum accepted latency for EMPI
Reset: 0x00
0x128
RW
RW
LMI2_LATENCY_GPDMA
[3:0] GPDMA_PRIORITY
[15:4] Reserved
LMI2 arbiter: GPDMA intitiator priority and latency
Defines priority for GPDMA
Reset: 0x1
0x130
RW
77/88
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