ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
7 Pin description
Pin names
Architecturally defined
reset state
Implementation reset state during and after
reset
Dir During reset Dir During reset
Following reset
NOTPLOCK
I
-
I/O
PCLK
I
-
I/O
NOTPREQ[0:3]
I
-
I/O
NOTPGNT[0:3]
O
1
I/O
PCLKOUT
O
Running
I/O
NOTPINTA
I/O
-
I/O
GPDMA pins
DACK0, DACK1
O
Z
I/O
DRAK0, DRAK1
O
Z
I/O
DREQ0, DREQ1
I
-
I/O
Serial communication interface with FIFO (SCIF) pins
SCI2
I
-
I/O
CTS1
O
Z
I/O
RXD0, RXD1
I
-
I/O
SCK0, SCK1
I
-
I/O
TXD0, TXD1
O
Z
I/O
Power, clocks and so on
NOTRST
I
-
I
IRL0:3, NMI
I
-
I
TMUCLK
I/O
-
I/O
LPCLKIN
I
-
I
CLKIN
I
-
I
LPCLKOSC, CLKOSC
O
Oscillator output
O
AUXCLKOUT
O
CLKIN
O
STATUS1:0
O
11
O
AUDATA0:3
O
00
O
AUDSYNC
O
1
O
AUDCLK
O
0
O
NOTASEBRK
I
-
I/O
DCLK, TCK, EADDR,TDI
I
-
I
NOTTRST,
I
-
I
TDO
O
Z
O
H
Z
Z
1111
Running
H
0
0
Z
H
H
H
H
H
(0)
(1)
H
H
0
Running
Running
CLKIN
11
00
0000
1
0
(1)
(0)
(0)
(1)
Z
Table 35: Pin reset states for ST40RA166
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